Ch 09 — Photonic Integration and Pluggable Optics

Photonic Integration and Pluggable Optics

The single biggest reason a 400G coherent transponder fits a router faceplate today — and a 1990s coherent transponder filled half a rack — is photonic integration. Lasers, modulators, hybrids, photodetectors, and waveguides have collapsed from discrete components on an optical bench into monolithic or hybrid chips fabricated with semiconductor processes. This chapter covers the three integration platforms that matter (Silicon Photonics, Indium Phosphide, Thin-Film Lithium Niobate), the integrated coherent transmit/receive assemblies built on them, the pluggable form-factor evolution from CFP to QSFP-DD800/OSFP800, the thermal and power constraints that bound any pluggable design, and the next step beyond pluggables: co-packaged optics.

Concept	What it says
Silicon Photonics (SiPh)	Photonic devices fabricated on silicon CMOS substrates. Strengths: process maturity from semiconductor manufacturing, unmatched economies of scale, easy electronics integration. Limitation: silicon does not emit light efficiently, so every SiPh coherent transmitter requires a separate III-V laser (typically InP) bonded to the silicon die.
Indium Phosphide (InP) PIC	Photonic Integrated Circuits on indium-phosphide substrates. Strength: direct bandgap supports monolithic laser integration on the same die as modulators and detectors. Limitation: lower wafer volume and higher cost per square millimetre than silicon, but mature for telecom for over two decades.
Thin-Film Lithium Niobate (TFLN)	Emerging modulator platform with the highest electro-optic bandwidth of any production technology (>100 GHz), enabling >140 Gbaud single-carrier signals. Today TFLN is used as a modulator chip combined with InP lasers and SiPh or InP detectors in heterogeneous assemblies; full TFLN integration is on the roadmap.

Modern Coherent Pluggable Architecture

A 400ZR or 800ZR pluggable is no longer a hand-assembled cluster of discrete components. The optical content is concentrated in two integrated assemblies:

flowchart LR
    subgraph PLUGGABLE ["Coherent pluggable (QSFP-DD / OSFP)"]
        ITLA["Micro-ITLA<br/>(narrow-linewidth<br/>tunable laser)"] --> TX["Integrated Tx<br/>(IQ modulator<br/>+ driver)"]
        TX --> SIGOUT["Signal out<br/>(LC or duplex MPO)"]
        SIGIN["Signal in"] --> RX["Integrated Rx<br/>(90 deg hybrid<br/>+ balanced PDs)"]
        ITLA --> RX
        RX --> ADC["DSP / ADC<br/>ASIC"]
        TX <-- TIA --> DSP_DAC["DSP / DAC<br/>ASIC"]
        ADC <--> DSP_DAC
        DSP_DAC <-->|"Electrical<br/>host I/F"| HOST["Router host<br/>(QSFP-DD / OSFP cage)"]
    end
    style ITLA fill:#D85A30,stroke:#993C1D,color:#fff
    style TX fill:#1D9E75,stroke:#0F6E56,color:#fff
    style RX fill:#1D9E75,stroke:#0F6E56,color:#fff
    style DSP_DAC fill:#E24B4A,stroke:#A32D2D,color:#fff
    style ADC fill:#E24B4A,stroke:#A32D2D,color:#fff
    style HOST fill:#378ADD,stroke:#185FA5,color:#fff

The integrated transmitter combines a micro-ITLA (tunable laser) with the IQ modulator and driver in one optical sub-assembly; the integrated receiver combines the 90° hybrid, balanced photodetectors, and trans-impedance amplifiers; the DSP ASIC sits next to both. The whole chain is driven by a single host electrical interface (CMIS-managed QSFP-DD or OSFP).

Three Integration Platforms

Silicon Photonics (SiPh)

Silicon photonics fabricates passive waveguides, ring resonators, Mach-Zehnder interferometers, and germanium photodetectors on silicon-on-insulator (SOI) wafers in a CMOS-compatible process flow. The platform’s strengths come directly from silicon CMOS: massive wafer volumes (12-inch / 300 mm wafers), mature lithography (down to deep-submicron features), and easy co-integration with electronic drivers and trans-impedance amplifiers either monolithically or by 3D stacking.

The single fundamental limitation is that silicon is an indirect-bandgap semiconductor and does not emit light efficiently. Every SiPh transmitter therefore needs a separate laser source — typically a III-V (InP) gain chip flip-chip bonded to the silicon waveguide, or a III-V die bonded onto silicon by heterogeneous integration. Once light is on the silicon waveguide, modulation, splitting, multiplexing, and detection all happen in silicon.

Indium Phosphide (InP)

Indium phosphide is a direct-bandgap III-V semiconductor on which lasers, semiconductor optical amplifiers, modulators, and photodetectors can all be fabricated monolithically on a single chip. This is its decisive advantage over silicon: a fully integrated coherent transmitter (laser + modulator + driver) and receiver (hybrid + photodetectors + TIA) can be a single InP die.

InP wafers are smaller (typically 4-6 inch), less mature, and more expensive per square millimetre than silicon, but the platform has been the workhorse of telecom-grade lasers and PICs for over two decades. Modern long-reach coherent products (long-haul transponders, premium pluggables) often use InP-based PICs for the integrated transmitter and SiPh or InP for the receiver.

Thin-Film Lithium Niobate (TFLN)

Lithium niobate (LiNbO₃) is the long-time gold standard electro-optic crystal — every legacy 10G/40G LiNbO₃ Mach-Zehnder modulator from the 1990s used bulk LiNbO₃. Thin-Film Lithium Niobate miniaturises this onto a < 1 µm-thick LiNbO₃ layer bonded to a silicon-dioxide buffer layer, which dramatically increases the electro-optic confinement and reduces the modulator drive voltage. The result is a modulator with electro-optic bandwidth in excess of 100 GHz — enough to drive 140+ Gbaud signals for next-generation 1.2T+ coherent.

TFLN today is used as a modulator chip in heterogeneous assemblies: an InP laser feeds light into a TFLN modulator; the modulated output goes to a SiPh or InP receiver on the partner side. Fully monolithic TFLN integration (laser + modulator + detector all on TFLN) is an active research direction.

Platform Comparison

Property	Silicon Photonics (SiPh)	Indium Phosphide (InP)	Thin-Film Lithium Niobate (TFLN)
Native laser integration	No (requires bonded III-V)	Yes (monolithic)	No (requires bonded III-V)
Modulator bandwidth	~30-50 GHz (Mach-Zehnder, depletion-mode)	~30-70 GHz (electro-absorption / MZM)	>100 GHz
Detector integration	Yes (Ge-on-Si)	Yes (monolithic InGaAs)	No (heterogeneous)
Wafer size / process maturity	200-300 mm CMOS	100-150 mm specialty	~100-150 mm specialty
Volume economics	Best	Moderate	Emerging
Best-suited role	Receivers, high-volume transmitters with bonded laser	Fully integrated transceivers, premium long-haul	Ultra-high-bandwidth modulators (800G+, 1.2T+)
Maturity for telecom	Production at scale (2015+)	Production at scale (2000+)	Early production (2024+)

Key Insight

No single platform dominates. Modern coherent optics are increasingly heterogeneous: an InP laser, a TFLN or InP modulator, a SiPh receiver, and a CMOS DSP — each fabricated on the platform best suited to its function and assembled into one package. The competitive frontier is in packaging and assembly, not in any single material system.

Integrated Coherent Transmitter and Receiver Assemblies

A modern integrated coherent transmitter packs the laser, IQ modulator, and modulator driver into a single sub-assembly:

• Micro-ITLA (Integrated Tunable Laser Assembly) — narrow-linewidth (~100 kHz) tunable across the C-band or C+L band, miniaturised from the ~100 cc desktop lasers of 2005 to a few cc today. Tunability is via a micro-controlled DBR or external-cavity laser.
• IQ Mach-Zehnder modulator — a nested Mach-Zehnder structure with two parallel sub-MZMs (one for I, one for Q) per polarisation. Modulator material is SiPh, InP, or TFLN.
• Linear modulator driver — high-bandwidth, low-noise driver electronics close-coupled to the modulator.

The integrated coherent receiver combines:

• 90° optical hybrid — a 4-port InP or SiPh waveguide interferometer.
• Balanced photodetector pairs — Ge-on-Si or InGaAs.
• Trans-impedance amplifiers (TIA) — linear, high-bandwidth amplifiers feeding the ADC.

In the highest-density designs, the transmit and receive sides plus the DSP ASIC sit on one package substrate. The next step is co-packaged optics, treated below.

Pluggable Form-Factor Evolution

The pluggable form factor has shrunk and densified over two decades while the line rate has grown by 80×. The timeline:

flowchart LR
    CFP["CFP<br/>2010<br/>~100G<br/>~30 W"] --> CFP2["CFP2<br/>2014<br/>~100-200G<br/>~12-20 W"]
    CFP2 --> CFP2_DCO["CFP2-DCO<br/>2017<br/>200G coherent<br/>~12-15 W"]
    CFP2_DCO --> QSFPDD["QSFP-DD<br/>2019<br/>400G (incl 400ZR)<br/>~14 W"]
    QSFPDD --> OSFP["OSFP<br/>2020<br/>400G premium<br/>~15-25 W"]
    OSFP --> QSFPDD800["QSFP-DD800<br/>2023<br/>800G<br/>~18-25 W"]
    QSFPDD800 --> OSFP800["OSFP800<br/>2024<br/>800G premium<br/>~20-30 W"]
    OSFP800 --> CPO["Co-packaged<br/>optics<br/>(2026+)<br/>on switch ASIC"]
    style CFP fill:#7F77DD,stroke:#534AB7,color:#fff
    style CFP2 fill:#7F77DD,stroke:#534AB7,color:#fff
    style CFP2_DCO fill:#7F77DD,stroke:#534AB7,color:#fff
    style QSFPDD fill:#1D9E75,stroke:#0F6E56,color:#fff
    style OSFP fill:#1D9E75,stroke:#0F6E56,color:#fff
    style QSFPDD800 fill:#BA7517,stroke:#854F0B,color:#fff
    style OSFP800 fill:#BA7517,stroke:#854F0B,color:#fff
    style CPO fill:#D85A30,stroke:#993C1D,color:#fff

Form factor	Year (mainstream)	Lane count × signalling	Aggregate	Power envelope
CFP	~2010	10 × 10 Gbaud NRZ (or 4 × 25 Gbaud)	100G	~30 W
CFP2	~2014	4 × 25-50 Gbaud NRZ/PAM4	100-200G	~12-20 W
CFP2-DCO (Digital Coherent Optics)	~2017	200G coherent	200G	~12-15 W
QSFP-DD	~2019	8 × 50 Gbaud NRZ/PAM4	400G (incl. 400ZR)	~14 W (class 8)
OSFP	~2020	8 × 50 Gbaud NRZ/PAM4	400G premium / 400ZR+	~15-25 W
QSFP-DD800	~2023	8 × 100 Gbaud PAM4	800G (800ZR class)	~18-25 W
OSFP800	~2024	8 × 100 Gbaud PAM4	800G premium / 800ZR+	~20-30 W
Co-packaged optics	2026+	Optics on switch ASIC substrate	25.6T+ per ASIC	Sub-pluggable per-bit (~1-2 pJ/bit)

Warning

Form-factor jumps are driven equally by electrical signalling (SerDes generation) and optical content. QSFP-DD and OSFP at 50 Gbaud per lane assume 56G or 112G SerDes on the host. QSFP-DD800 and OSFP800 require 100 Gbaud PAM4 per lane — a SerDes generation only widely shipping in 2023+. A pluggable’s form factor implies a host-side SerDes requirement that not every router supports.

Thermal and Power Budget Engineering

A coherent pluggable has hard physical limits. The DSP ASIC is the largest power consumer (5-15 W depending on rate and process node); the laser, modulator drivers, and TIAs add several more watts. Total power for a 400ZR pluggable is ~14-18 W; for 800ZR it climbs to ~20-25 W.

Thermal dissipation is the binding constraint. In QSFP-DD the heat sink is on the host cage (the cage’s fins are top-side). In OSFP the heat sink is integrated on the module itself. Both rely on forced-air cooling from the host platform; both have qualified maximum dissipation per thermal class.

Rate / family	Typical pluggable power	Practical thermal limit (host-class dependent)	Consequence of exceeding
400ZR (QSFP-DD class 8)	~14 W	Most modern routers qualified	Module throttles or fails
400ZR+ (high-power)	~16-22 W	Requires high-thermal-class cage	Degraded reach, FEC pressure
800ZR	~18-25 W	Few platforms qualified at top end (2024+)	Errors, frequency drift
800ZR+	~22-30 W	OSFP800 only, premium thermal class	Same

Rule of Thumb

Every pluggable generation drops the per-bit power by roughly 30-40% (e.g. ~30 W / 100G in CFP → ~3.5 W / 100G in QSFP-DD 400ZR → ~2.5 W / 100G in QSFP-DD800 800ZR). The pace of that improvement, not absolute power, is what enables each form-factor doubling.

Co-Packaged Optics — Beyond Pluggables

The next step beyond pluggable optics is co-packaged optics (CPO): photonic engines mounted on the same substrate as the switch ASIC, with optical fibres exiting the package directly. Pluggables disappear — the switch faceplate is just a fibre connector array.

flowchart TB
    subgraph TODAY ["Today: pluggable"]
        ASIC1["Switch ASIC<br/>25.6T or 51.2T"] -->|"Long electrical<br/>SerDes traces"| PLUG1["QSFP-DD800 / OSFP800<br/>~20-25 W per port<br/>~16-32 ports"]
        PLUG1 --> FIBRE1["Faceplate fibre"]
    end
    subgraph CPO_SUBGRAPH ["Co-packaged optics"]
        ASIC2["Switch ASIC<br/>25.6T or 51.2T"] <-->|"Short xPU<br/>traces"| ENGINE["CPO engines<br/>on substrate<br/>around ASIC"]
        ENGINE --> FIBRE2["Direct fibre out"]
    end
    style ASIC1 fill:#E24B4A,stroke:#A32D2D,color:#fff
    style ASIC2 fill:#E24B4A,stroke:#A32D2D,color:#fff
    style PLUG1 fill:#1D9E75,stroke:#0F6E56,color:#fff
    style ENGINE fill:#D85A30,stroke:#993C1D,color:#fff
    style FIBRE1 fill:#7F77DD,stroke:#534AB7,color:#fff
    style FIBRE2 fill:#7F77DD,stroke:#534AB7,color:#fff

Two driving forces:

1. SerDes power scaling. Every pluggable generation requires faster electrical SerDes from the ASIC to the pluggable cage. SerDes power per bit has been falling slower than optical power per bit; on 51.2T+ ASICs the SerDes accounts for an unsustainable fraction of total package power.
2. Lane count scaling. A 51.2T ASIC at 800G per port needs 64 ports — a faceplate density that pluggable packaging cannot deliver at acceptable power and signal-integrity margins.

CPO short-circuits the SerDes by integrating the optical engines onto the ASIC substrate. The electrical signal travels millimetres instead of inches; SerDes power drops; faceplate density rises. The penalty is loss of the field-replaceable-pluggable model — if an optical engine fails, the whole switch may need attention rather than a hot-swap module.

Key Insight

CPO is to pluggables what pluggables were to dedicated transponders: a step-function in integration density that trades modularity for power and density. As 51.2T and 102.4T switch ASICs ship in the late 2020s, CPO is the credible path; pluggables remain the dominant model below those scales.

Summary

Photonic integration is what made pluggable coherent optics possible. Silicon Photonics, Indium Phosphide, and Thin-Film Lithium Niobate are the three platforms in production today, and modern coherent pluggables increasingly combine them heterogeneously: InP laser + TFLN/InP modulator + SiPh receiver + CMOS DSP. Form factors have evolved from CFP (~30 W, 100G) through CFP2-DCO and QSFP-DD/OSFP (~14-25 W, 400-800G) toward QSFP-DD800/OSFP800 (~20-30 W, 800G+). Thermal envelopes are the hard ceiling of any pluggable design. The next step — co-packaged optics — moves the photonics onto the switch ASIC substrate to escape the SerDes-power wall at 51.2T+ scales.

See Also

• Modulation, Coherent Detection, and DWDM Architecture
• Coherent DSP Internals
• Open and Disaggregated Optical, and IPoDWDM

References

Standards and form-factor MSAs

1. QSFP-DD MSA specification (including QSFP-DD800). https://www.qsfp-dd.com/
2. OSFP MSA specification (including OSFP800). https://osfpmsa.org/
3. CFP MSA — Centum-form Pluggable. http://www.cfp-msa.org/
4. OIF Common Management Interface Specification (CMIS). https://www.oiforum.com/documents/
5. OIF 400ZR Implementation Agreement (OIF-400ZR-01.0). https://www.oiforum.com/documents/
6. OIF 800ZR Implementation Agreement (OIF, ongoing). https://www.oiforum.com/documents/
7. IEEE 802.3 (including 802.3bs 400 GbE, 802.3ck, 802.3df 800 GbE). https://standards.ieee.org/standard/802_3-2022.html

Industry consortia

8. Co-Packaged Optics Collaboration — Optical Internetworking Forum / OCP CPO. https://www.opencompute.org/wiki/Networking/CPO

Books

9. L. Chrostowski, M. Hochberg, Silicon Photonics Design: From Devices to Systems, Cambridge University Press, 2015.
10. R. Nagarajan et al., “Large-scale Photonic Integrated Circuits,” IEEE J. Sel. Top. Quantum Electron. 11, 50 (2005).

Papers

11. C. Wang, M. Zhang, X. Chen et al., “Integrated lithium niobate electro-optic modulators operating at CMOS-compatible voltages,” Nature 562, 101 (2018). [TFLN modulator]
12. D. Thomson et al., “Roadmap on silicon photonics,” J. Opt. 18, 073003 (2016).
13. K. Roberts et al., “Beyond 100 Gb/s: Capacity, Flexibility, and Network Optimization,” J. Lightwave Technol. 35, 1 (2017).
14. R. Stabile, A. Rohit, K. A. Williams, “Monolithic active-passive 16x16 optoelectronic switch,” Opt. Lett. 37, 4666 (2012). [InP PIC]